1. Field of the Invention
The invention relates to a circuit unit for data bit inversion of a data burst read out from a memory module, in particular for DDR-SDRAM (Double Data Rate Synchronous Dynamic Random Access Memories).
2. Description of the Prior Art
FIG. 1 shows a computer system according to the prior art in which a memory chip and a controller chip exchange data via a common data bus. The increasing speed of computer processors and/or controllers requires a correspondingly higher speed in the case of instances of memory access and/or faster memory modules. The memory module and the processor are clocked via a clock signal CLK.
Various generations of RAM memories have been developed whose access rate has risen continuously. The time intervals in which new data read out from the memory cell array or to be written are present at the data inputs/outputs of the corresponding memory module have been shortening continuously. So-called DDR-SDRAMs with a double data rate have been developed starting from synchronous dynamic RAMs (SDRAMs). Such DDR-SDRAMs supply data twice as quickly as conventional SDRAMs. However, with DDR-SDRAMs there is no doubling of the clock pulse, but rather two actions are instigated in one clock pulse. Whereas conventional SDRAMs are always synchronized only relative to the rising clock-pulse edge of the bus clock pulse, in the case of a DDR-SDRAM both the rising and the falling clock-pulse edge are used for data transmission.
The data transfer rate of a DDR-SDRAM, which corresponds to double the clock frequency, is virtually 2 GHz for clock frequencies in the range from 800 MHz to 1 GHz.
Data are read out as a data burst when the memory module is accessed for reading, each data burst consisting of a number of data words which in each case comprise a predetermined number n of data bits. The number of the data bits within a data word corresponds to the bus width N of the data bus. 4 data words (m=4) each comprising 8 bits (n=8), for example, are read out in a data burst. FIG. 2 shows how a data burst is read out from an SDRAM according to the prior art. The inductive and capacitive couplings increase because of the increasing operating frequency, and so instances of data falsification occur. With increasing operating frequency, it becomes ever more difficult to transfer the data from the memory module to the controller. The noise on the data lines of the data bus constitutes one limitation here. The noise limits the validity period of the data and reduces the so-called data eye size. The more switching processes and/or data transfers that occur on the data lines, the greater the rise in the instances of data falsification, that is to say the bit error rate (BER) rises.
FIG. 3 shows the transfer of a data burst during a read access from a memory module to a controller in the case of a conventional data processing system according to the prior art. In the example illustrated in FIG. 3, a data burst with 8 data words each comprising 8 bits is transferred. After the memory module has received a read command (RD) from the controller, via a control bus, it transfers a data burst after a certain latency to the controller via the data bus. In the example illustrated, the memory module transfers the following sequence of data words, specifically: FF, 00, 00, EF, FF, 00, 02, FF. The number of bits occurring in this case, which change their value during a transition from a data word to the next data word, is specified in FIG. 3. All the bits of the data word change their logic value in the case of transition from the first data word (FF) to the second data word (00). In the case of the next transition, none of the bits changes its logic value. Seven bits change their logic value in the case of a transition from the data word 00 to the data word EF.
In order to limit the noise caused by this switching, a so-called data bit inversion (DBI) is introduced in the case of the GDDR4 (Graphics Data Double Rate) Standard. Here, before the transfer of the data a check is made internally in the memory chip with the aid of a decoder as to how many data bits of a data word have been changed relative to the data bits of the preceding data word transferred directly previously. If the number of the changed data bits exceeds half the data bits of the data word, all the data bits of the subsequent data word are transferred in an inverted fashion to the controller on the data bus. The inversion of the data bits of the data word is indicated to the controller by additional transfer of a DBI flag. FIG. 4 shows such a data bit inversion according to the prior art and for the example illustrated in FIG. 3.
Since more than half, specifically eight data bits, change the data state between the two first data words (FF, 00), the second data word is transferred in an inverted fashion as FF. Since likewise more than half the data bits change their state between the inverted data word FF and the next data word 00 to be transferred, the third data word is also transferred in an inverted fashion and as FF to the controller. Since only one data bit transition, and therefore less than half the number of the data bits, is inverted within a data word between the third inverted transferred data word and the next data word EF to be transferred, the fourth data word EF is transferred without inversion to the controller, etc . . . As may be learned from FIG. 4, the number of the data bit transfers or switching bits is substantially less than in the case of a data transfer without data bit inversion as illustrated in FIG. 3. FIG. 4 also shows the data bit inversion flag DBI, which is transferred in a parallel fashion and indicates to the processor whether the received data word has been inverted or not.
FIG. 5 shows a circuit unit for data bit inversion of a data burst, read out from a memory module, according to the prior art. The entire data burst read out from the memory cell array is firstly buffered in a burst buffer. For example, m=4 data words each having n=8 data bits are buffered in the burst buffer. An associated decoder, for example m=4 decoder, is provided for each data word DW within the burst buffer. Each decoder compares the data bits of a data word with those data bits of the preceding data word.
FIG. 6 shows a circuit design of a conventional decoder such as is used in the data bit inversion unit according to the prior art in accordance with FIG. 5. Upon reception of an enable signal (EN), the data word read out from the burst buffer is loaded into a register. At the same time, the preceding data word (DWi-1) of the data burst is likewise loaded into a register as reference data word. An XOR logic circuit compares the data content of the two registers in a bitwise fashion. A counter counts the number of the different data bits. A comparator compares the number of the different data bits in the two data words with half the number of data bits within a data word. If, for example, the number of data bits within a data word is 8 bits, the comparator compares the number of different data bits that has been found with the value 4. If the number of the different data bits is higher than half the number n of data bits within the data word, a data bit inversion flag (DBI) is set by the comparator. The DBI flag controls a multiplexer of the decoder internally. The data word DWi buffered in the first register is switched through by the multiplexer either in an inverted or uninverted fashion. When the DBI flag is set by the comparator, this is followed by a bitwise inversion of the data bits. Once the comparator is finished with the comparison, it passes a ready indicator control signal on to the next decoder within the cascade.
As can be seen from FIG. 5, the data words which are output by the decoders are applied to a parallel-to-serial converter which is activated by the ready control signal from the last decoder within the cascade. The parallel-to-serial converter converts the received data words and the associated data bit inversion flags into a serial data stream. A data bus is used to output a data burst consisting of m data words, which each have a bit length n, and also m data bit inversion flags to the controller. As can be seen from FIG. 5, the decoders in the data bit inversion unit based on the prior art operate in serial fashion. The decoders are connected up as a cascade, that is to say a decoder i within the cascade always requires the output value from the preceding decoder i-1 within the cascade as reference data word in order to be able to make the necessary comparison. The parallel-to-serial converter P/S cannot start to convert the data words present in parallel form into a serial sequence until after the last decoder DECm within the cascade has finished the comparison and activates it by means of an enable signal. The waiting time is thus m times the necessary decoding time for a decoder i within the cascade:Twait=m·TDEC 
If the decoding time for a decoder DECi within the cascade is one nanosecond, for example, and if a data burst comprises m=4 data words, the waiting time is 4 ns.
The increased waiting time results in an unwanted delay and the memory access time for data within the memory module. This has an overall negative effect on the system performance. The serial processing during the DBI assessment results in a long time delay for the parallel data transfer, since it is necessary to wait until the decoding of the last data word within the data burst has ended. All the data which have already been processed have to wait for this time until they can be processed further in parallel.